Verification is becoming the critical path.
As chip complexity rises, teams spend more time writing tests, triaging regressions, and closing coverage. The industry is shipping later despite larger verification teams and better tools.
First-silicon success
% of IC/ASIC projects whose first silicon worked, by study year
Sources
Siemens EDA and Wilson Research Group functional verification studies, IC/ASIC projects. 2020 and 2022 are from the text of the 2020 and 2022 studies, 2024 from the 2024 IC/ASIC Functional Verification Trend Report, and 2026 from the 2026 study.
On schedules: the 2024 report finds 75% of IC/ASIC projects behind schedule, against about 66% historically, and the 2026 study about three in four IC/ASIC and FPGA projects missing their original schedules (Foster, 2026).
The 2024 and 2026 studies recruited participants differently from earlier years (Methodology), so they compare most directly with each other. Treat these results as industry trend indicators, not proof that verification alone causes respins.
An AI teammate for chip verification.
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Akrida reads the spec you already have, as PDF or Markdown, and pulls out each requirement it can check, including behavior the spec implies but never numbers.
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It plans a check and coverage points for each requirement, then writes the testbench and the tests aimed at them. You can review and edit the plan before the testbench is written.
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The tests run on Verilator today, and support for your existing EDA tools is coming soon. Akrida separates design bugs from testbench issues, backs each finding with its log and waveform, and can file design bugs as GitHub issues.
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Coverage gaps aim the next round of tests, and the loop runs again. Each round reports its coverage, until it meets your target or reaches its round limit.
Questions
Can I try Akrida?
We are working with a small number of early evaluation partners. Request a demo to discuss running Akrida on a real verification task.
Does Akrida replace my verification team?
No. Akrida is built to take on repetitive verification work, including test planning, test generation, regression investigation, and coverage analysis. Engineers stay in control of what is tested, how findings are reviewed, and what gets fixed.
Where does my design data go?
In the hosted version, your design is simulated on Akrida’s servers. The AI model never sees your RTL: it works from your specification, your design’s port list and the simulation results. The MVP’s current deployment model and data handling will be scoped with each evaluation partner. We are building toward customer-controlled, on-prem deployments for teams whose design data must remain inside their environment.
What does Akrida work with?
Akrida is designed to work alongside the verification tools and workflows teams already use. Today it takes a specification as PDF or Markdown and RTL in Verilog or SystemVerilog, runs its tests on Verilator, and can file design bugs as GitHub issues. Support for existing EDA tools such as Xcelium, VCS and Questa is coming soon.
Run Akrida on a real verification task.
Thanks.
We will follow up to learn about your verification flow and whether Akrida is a fit for an evaluation.